An Area-Efficient Carry Select Adder Design by using 180 nm Technology
نویسندگان
چکیده
منابع مشابه
An Efficient Carry Select Adder Design by using different Technologies
According to the modern research the rapid development of portable electronics is forcing the designers to elevate the existing designs for better performance. Addition is the crucial arithmetic operation used in various applications like, Digital signal processors, ALUs, math processor and in various other scientific applications. In this paper, we proposed the 1-bit CSA with gates having diff...
متن کاملDesign of Area and Power Efficient Modified Carry Select Adder
Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumpti...
متن کامل128 Bit Low Power and Area Efficient Carry Select Adder
Carry Select Adder (CSLA) which provides one of the fastest adding performance. Traditional CSLA require large area and more power. Recently a new CSLA adder has been proposed which performs fast addition, while maintaining low power consumption and less area. This work mainly focuses on implementing the 128 bit low power and area efficient carry select adder using 0.18 μm CMOS technology. Base...
متن کاملHard ware implementation of area and power efficient Carry Select Adder using reconfigurable adder structures
In data processing processors, adder is a basic digital circuit. To perform any arithmetic operation, addition is the basic operation to perform. To compute fast arithmetic operations adder must be fastest. CSLA is the fastest adder when compare to RCA and CLA. From the structure of CSLA it is observed that there is a scope to reduce area further so that power can be lowered [3-4]. This paper p...
متن کاملAn area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit
This paper presents a highly area-efficient CMOS carry-select adder (CSA) with a regular and iterative-shared transistor structure very suitable for implementation in VLSI. This adder is based on both a static and compact multi-output carry look-ahead (CLA) circuit and a very simple select circuit. Comparisons with other representative 32-bit CSAs show that the proposed adder reduces the area b...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Advanced Computer Science and Applications
سال: 2013
ISSN: 2158-107X,2156-5570
DOI: 10.14569/ijacsa.2013.040118